A conventional form of semiconductor memory is random access memory (RAM) in which information (data values) is stored as electrical charges in an array (columns and rows) of storage cells. Dynamic RAM (DRAM) storage cells are extremely small, but have only relatively short-term storage capability and must be "refreshed" periodically. Static RAM (SRAM) storage cells have the capability of retaining data values as long as power is applied without needing to be refreshed. Interface logic controls the writing of data to and the reading of data from the memory array. Data is typically stored as bytes, or some multiple thereof, each byte representing eight bits of binary information. For example, a given single data value may be 8, 16, 32, 64 or more binary bits "wide", requiring corresponding 8, 16, 32, 64 or more storage cells in the memory array.
"Conventional" memories for digital information storage come in a wide variety of technologies including, but not limited to:
Fuse-link ROM: Information is stored in an array of fuses (which are normally shorted and are blown "open") or anti-fuses (which are normally open and are programmed "closed") PA1 EPROM (Erasable Programmable Read-Only-Memory): A form of Read-Only-Memory in which information is stored in an array of capacitors with very low leakage. Data stored in these capacitors will be retained for 10 years or more without reprogramming. These memories are often erasable by exposure to Ultraviolet light--also known as UV EPROM) PA1 Mask ROM: A form of ROM where the information pattern is "masked" right onto the chip at the time of manufacture PA1 Flash ROM: A form of EPROM based upon conventional UV EPROM technology but which is provided with a mechanism for electrically pre-charging selected sections of the capacitive storage array, thereby effectively "erasing" all capacitive storage cells to a known state. PA1 Dynamic RAM: DRAM or Dynamic Random Access Memory--a form of read/write memory wherein information is stored in a high-density, low-overhead array of capacitive storage cells. These cells are extremely small but have only relatively short-term storage capability and must be "refreshed" periodically. Hence, the "dynamic" name. PA1 Static RAM: SRAM or Static Random Access Memory--a form of read-write memory in which data is stored in cells which retain their data values indefinitely as long as power is applied. Data is lost when power is removed. PA1 Non-volatile RAM: Any form of read/write memory which retains data values even when power is removed. This form of memory is often implemented by providing long-term battery backup for conventional static RAM.
All of the memories types listed above are "random access" in that storage elements may be accessed in any arbitrary order. However, in common use, the term "Random Access Memory" implies that the memory can be both read and written. Electrically erasable ROM technologies tend to blur this distinction since they can be erased and re-written. In an attempt to emphasize the re-writable, non-volatile storage aspects of their Flash memory systems, some system designers have been known to refer to such memories as Flash RAM.
Conventional memories store information as a series of "bits" or binary digits which can take on one of two different values. These values are arbitrarily assigned the values 1 and 0, and are grouped together to represent larger numbers. For example, the binary number 110 (one,one,zero) represents the decimal number 6 (six).
Most static RAM memories are built around a latching cell which behaves much as a bi-stable latch or Flip-Flop. This latching cell can be caused to assume one of two active states, thereby providing the required two-valued storage capability.
Dynamic RAMs and EPROMS, however, are usually built around capacitive storage cells in which information is stored by controlling the amount of charge applied to capacitive storage elements within the cells. A "sense amplifier" is used to determine whether or not the charge on the storage element is above or below a preset threshold, thereby returning one of two possible results (i.e., a "one" or a "zero") for each capacitive storage element.
The maximum density of conventional memory is dictated by the size of the individual storage elements and the number of storage elements that can be integrated onto a single chip. Until recently, the only practical way to increase memory density has been to shrink the line width and transistor sizing (process geometry), a fairly incremental process heavily limited by photolithography and stepper tools developed by semiconductor equipment manufacturing companies.
A recent development in semiconductor memory is known as "multilevel technology" ("MLT"). The underlying premise of MLT memory is that a significant increase in memory density could be obtained if it were possible to store more information in each storage element of a conventional memory. Unfortunately, the storage elements (cells) of many conventional memory structures (e.g., Static RAM) are inherently restricted by their very nature to assuming only one of two possible (binary) states. Certain conventional memory structures do, however, lend themselves to greater storage density than can be achieved using conventional binary, two-level storage techniques. Some of the best candidates for this increased density are memory technologies such as DRAM and Flash ROM which use capacitive storage elements.
The information in capacitive-based storage elements is stored based upon the amount of charge on a capacitive storage cell. It seems reasonable then, that by quantizing information into units greater than binary units (e.g., 4-level or 8-level units), and providing the ability for charge to be stored in the capacitive storage cells in a greater (i.e, than two) number of discrete levels, that it would be possible to dramatically increase the storage capacity of such memories. In fact, companies such as Intel have already recently demonstrated the feasibility of such multilevel storage techniques.
However, there are some difficulties inherent with these techniques. It is, for example, more difficult to control the application of multiple discrete units of charge to a capacitive cell than it is simply to fully charge or fully discharge the cell. In attempting to store a value into a multilevel cell in a multilevel format, it must be ensured that the intermediate values (i.e., values between full-charge and full-discharge) are accurately and retrievably represented.
Even ignoring the problems of storing multilevel information, increasing the number of discrete values (units of charge) which can be stored in a capacitive storage cell can adversely affect cell readback in a variety of ways. For example, a greater number of discrete values reduces the "noise margin" of the cell as compared to two-level (binary) storage, making the storage element more prone to erroneous readout. Additionally, the storage-retention times specified for most capacitor-based ROM technologies are based upon the time it takes for natural capacitive "leakage" to degrade the stored charge to the point where the two-level readback threshold is no longer sufficiently reliable. In a multilevel storage cell, this retention time would be reduced due to correspondingly reduced charge-decay "margins" around multilevel thresholds. Because of the unreliable nature of current MLT memory, its use has tended to be limited to fault tolerant applications such as audio and video transmission wherein the human viewer or listener is tolerant of (insensitive to) a certain amount of "noise". Generally speaking, reliability is simple to quantify -namely, by determining whether values which have been stored are retrievable without corruption. For example, it would be of little use in the digital signal processing (DSP) arena to store (write) a value of THREE, and retrieve (read) a value of FOUR. These and other problems related to providing reliable multilevel storage dominate current research in the field of MLT memories.
The aforementioned capacitive storage element and multilevel charge storage is only one possible technique for implementing multilevel technology. In the more general case, multilevel memory technology can be built around any storage technique which permits more than two discrete values (states) to be stored in a single storage cell. A memory (storage) density benefit is ultimately realized only if the physical size of the multilevel storage cell is less than the aggregate size of the multiple conventional storage cells which would be required to store the same amount of information that could be reliably stored in a single MLT memory cell.